HUAWEI-CESC-MA5100-MIB

HUAWEI-CESC-MA5100-MIB Download

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OID list for HUAWEI-CESC-MA5100-MIB

hwMusaCescCfgTable
Board config table
hwMusaCescCfgEntry
Board config table entry
hwMusaCescWorkMode
Working mode of CES board
hwMusaCesc16MTDMBus0
TDM bus 0 of CES board
hwMusaCesc16MTDMBus1
TDM bus 1 of CES board
hwMusaCesc16MTDMBus2
TDM bus 2 of CES board
hwMusaCesc16MTDMBus3
TDM bus 3 of CES board
hwMusaCescPortCfgTable
E1 port config table
hwMusaCescPortCfgEntry
E1 port config table entry
hwMusaCescPortIndex
CES port index
hwMusaCescPortWorkMode
The working mode of E1 port
hwMusaCescPortClockMode
Clock mode of E1 port
hwMusaCescPortSignalType
Signal type of E1 port
hwMusaCescPortFrameVerifyMode
Frame verify mode of E1 port
hwMusaCescPortTimeSlotBMP
Timeslot bitmap of E1 port
hwMusaCescPortWarningStatus
bit0- LOS bit1- LOF bit2- RRA bit3- LMF bit4- AIS
hwMusaCescPortUtopiaStatus
UTOPIA port state( normal(1), test(2), idle(3), noinstall(4), failure(5), blocked(6)
hwMusaCescPortLiuStatus
LIU port state (normal(1), test(2), idle(3), noinstall(4),failure(5),blocked(6),localtest(11),remotetest(12),tslocal(13)
hwMusaCescPortBlock
To block or unblock the E1 port
hwMusaCescPortV35CfgTable
V35 port config table
hwMusaCescPortV35CfgEntry
V35 port config table entry
hwMusaCescPortV35NValue
N value of V35 port
hwMusaCescPortV35ClockMode
Clock mode of V35 port
hwMusaCescPortV35BlockStatus
To block or unblock the V35 port
hwMusaCescPortV35ReversePhase
Inverse the clock of V35 port
hwMusaCescPortV35WarningStatus
Alarm state of V35 port
hwMusaCescPortV35Status
Port state of V35
hwMusaCescChnlStatisTable
Statistics table of CES SDT channel
hwMusaCescChnlStatisEntry
Statistics table entry of CES SDT channel
hwMusaCescChnlIndex
SDT channel Index
hwMusaCescChnlStatisCounter0
Discard cells due to output queue
hwMusaCescChnlStatisCounter1
not used
hwMusaCescChnlStatisCounter2
Cells that are passed to framer interface
hwMusaCescChnlStatisCounter3
Times SDT start of structure changes phase upstream
hwMusaCescChnlStatisCounter4
Discard downstream cells with invalid SN/SNP
hwMusaCescChnlStatisCounter5
End of reassembly buffer overflow
hwMusaCescChnlStatisCounter6
Downstream cells with invalid SN/SNP
hwMusaCescChnlStatisCounter7
SC out of sequence
hwMusaCescChnlStatisCounter8
Downstream misinserted cells detected by SC algorithm
hwMusaCescChnlStatisCounter9
Downstream cells discarded by SC algorithm
hwMusaCescChnlStatisCounter10
Rejected SDT pointer due to parity error
hwMusaCescChnlStatisCounter11
SC cycles with no SDT pointer field or more than one pointer field
hwMusaCescChnlStatisCounter12
End of reassembly buffer underflow
hwMusaCescChnlStatisCounter13
Insert starvation cells due to reassembly buffer underflow
hwMusaCescChnlStatisCounter14
Times ATM start of structure out of sync with port start of structure
hwMusaCescChnlStatisCounter15
Downstream lost cells detected by SC algorithm
hwMusaCescChnlStatisOper
Clear CES SDT channel statistics
hwMusaCescPortStatisTable
Statistics table of CES UDT/UNI port(UNI port only use from counter 0 to counter 4)
hwMusaCescPortStatisEntry
Statistics table entry of CES UDT/UNI port
hwMusaCescPortStatisCounter0
Discard cells due to output queue
hwMusaCescPortStatisCounter1
Received cells with correctable HEC errors (UNI)
hwMusaCescPortStatisCounter2
Received cells with non-correctable HEC errors (UNI)
hwMusaCescPortStatisCounter3
Times cell delineation SYNC state is left (UNI)
hwMusaCescPortStatisCounter4
Discard cells due to ATM transmit buffer overflow (UNI)
hwMusaCescPortStatisCounter5
End of reassembly buffer overflow (UDT)
hwMusaCescPortStatisCounter6
Downstream cells with invalid SN/SNP (UDT)
hwMusaCescPortStatisCounter7
SC out of sequence (UDT)
hwMusaCescPortStatisCounter8
Downstream misinserted cells detected by SC algorithm (UDT)
hwMusaCescPortStatisCounter9
Downstream cells discarded by SC algorithm (UDT)
hwMusaCescPortStatisCounter10
Rejected SDT pointer due to parity error (UDT)
hwMusaCescPortStatisCounter11
SC cycles with no SDT pointer field or more than one pointer field (UDT)
hwMusaCescPortStatisCounter12
End of reassembly buffer underflow (UDT)
hwMusaCescPortStatisCounter13
Insert starvation cells due to reassembly buffer underflow (UDT)
hwMusaCescPortStatisCounter14
Times ATM start of structure out of sync with port start of structure (UDT)
hwMusaCescPortStatisCounter15
Downstream lost cells detected by SC algorithm (UDT)
hwMusaCescPortStatisOper
Clear CES UNI/UDT port statistics
hwMusaCescPortMaintTable
Maintenace table of CES port
hwMusaCescPortMaintEntry
Maintenace table entry of CES port
hwMusaCescPortMaintLoop
The looping test mode of CES port
hwMusaCescPortMaintOper
The oprating of looping test mode
hwMusaCescSingleTimeslotId
The timeslot number of single timeslot looping test (only for SDT port)

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