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cwacsHighEgrRcvEFCI1
cwacs High Egr Rcv EFCI1
1.3.6.1.4.1.351.150.2.1.1.1.1.67
The number of valid EFCI=1 cells in the egress direction of this Channel before the class of service queue. This counter carries upper 32-bits of cwacsHCEgrRcvEFCI1. The lower 32-bits will be present in cwacsEgrRcvEFCI1.
Back to CISCO-WAN-ATM-CONN-STAT-MIB MIB page.
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